As is well known to those having skill in the art, integrated circuit dynamic random access memories (DRAM) comprise an array of memory cells, each of which includes a transistor and a capacitor. In order to increase the cell capacitance, it is known to increase the surface area of the capacitor plates, reduce the thickness of the dielectric material, and/or use a dielectric material having a high dielectric constant, such as tantalum dioxide.
One technique for increasing the surface area of the capacitor plates, uses a "stacked cell" process rather than a planar process. Unfortunately, as the integration density of DRAMs continues to increase, the use of stacked cells may reduce the process margin during manufacture of the DRAM. These reduced process margins may make it difficult to increase the integration density of the DRAM.
As the integration density of DRAMs continues to increase, the cell capacitance generally tends to decrease as the memory cell area is reduced. Reduced capacitance may reduce the ability to accurately read data from the memory cell, and may increase the soft error rate. DRAM operation may become difficult at low voltage without excessive power consumption.
For example, if a 64 megabit DRAM includes a memory cell area of about 1.5 .mu.m.sup.2 using a two dimensional stacked memory cell, it may be difficult to obtain sufficient capacitance even when using a material having a high dielectric constant. Thus, a three dimensional stacked capacitor has been proposed to increase the capacitance. A conventional method for manufacturing an integrated circuit memory device will now be described with reference to FIGS. 1 through 3.
Referring to FIG. 1, a transistor having a drain region 5, a source region 7 and a gate electrode 9 is formed on an active area defined by a field oxide film 3 which acts as an inactive area of a semiconductor substrate 1. Also, an insulating film 11 for insulating the gate electrode 9 is formed in a predetermined shape. Next, a first interlayer insulating film 15 is formed on the entire surface of the resultant structure, and partially etched to form a bit line contact hole. Then, a conductive material is deposited to fill the bit line contact hole, and is patterned to form a buried bit line 13 connected to the drain region 5.
Subsequently, a second interlayer insulating film 15' is formed on the structure on which the bit line 13 and the transistor are formed. Thereafter, the first and second interlayer insulating films 15 and 15' which are stacked on the upper part of the source region 7, are partially etched to form a storage node contact hole 17.
Referring to FIG. 2, a polysilicon film 19 is formed so as to bury the storage node contact hole 17 and have a predetermined thickness on the second interlayer insulating film 15'. A photoresist pattern 21 for forming a storage electrode is formed on the polysilicon film 19.
Referring to FIG. 3, a storage electrode 19a is formed by partially etching the polysilicon film 19 using the photoresist pattern 21 as an etch mask. Also, a dielectric film 23 and a conductive plate electrode 25 are formed on the entire surface of the silicon substrate 1 on which a storage electrode 19a is formed. Thus, a memory device having a capacitor is manufactured.
However, according to the above-described conventional method for manufacturing a capacitor of a memory device, the first and second interlayer insulating films 15 and 15', which insulate the bit line 13 electrically connected to the drain region 5 of the transistor, may increase the step difference between the storage node 19a and source region 7. Therefore, in forming a contact hole for electrically connecting the storage node 19a to the source region 7, an overlay margin or focus depth may be reduced. Accordingly, the probability of generating a misalignment of the storage node and the source region may increase, or the source region may not be fully opened, thereby reducing the performance of the device.